Changmin Lee

  • Senior Engineer (Mar. 2018 to Current)
    Memory Business, Device Solutions Division, Samsung Electronics – Hwaseong-si, South Korea
  • E-mail: exahz AT yonsei DOT ac DOT kr


  • Ph.D. in Electric and Electrical Engineering (Mar. 2011 to Feb. 2018)
    Yonsei University – Seoul, South Korea
  • B.S. in Electric and Electrical Engineering (Mar. 2005 to Feb. 2011)
    Yonsei University – Seoul, South Korea

Work Experience

  • Full-Time Summer Intern (Jul. to Aug. 2012)
    Video Service Development Team, NAVER Corp. – Seongnam-si, South Korea
    Development of a parallel H.264 encoder running on multiple GPUs.


  • “Multicore Systems Design: Multithreaded Programming Practices,” Samsung Advanced Technology Training Institute, Suwon-si, Gyeonggi-do, South Korea, Dec. 15, 2015.


  • Development of HW Architecture and IPs for Next-Generation Mobile Intelligence, Samsung Electronics, 2016.
  • An Analysis of Processor and DRAM Controller’s Characteristics for Understanding System’s Behaviors, Samsung Electronics, 2014.
  • Development of Mobile System Benchmarks and Bottleneck Analysis Tools for Evaluating User Experience, Samsung Electronics, 2013.
  • Development of Power-Awareness Android Binder Monitoring and Enhancement Techniques, LG Electronics, 2013.
  • Network Adaptive Video Streaming Solution for Mobile Environment, NHN Corporation, 2013.
  • Development of Web Application Server and Bottleneck Analysis, Samsung Electronics, 2012.
  • Load-Balancing of Video Transcoding with GPU-Accelerated Encoding and Computation Offloading, NHN Corporation, 2012.
  • Development of Smart Home Gateway Using Profiling Information, Samsung Electronics, 2011.

Research Interests

  • Current research interest is enabling next-generation memory devices (architectural optimization for new memory technologies and persistent memory).



  • Changmin Lee and Won Woo Ro, “Simultaneous and Speculative Thread Migration for Improving Energy Efficiency of Heterogeneous Core Architectures,” IEEE Transactions on Computers, Vol.67, No.4, pp. 498-512, Apr. 2018.


  • Sangheon Kwon, Kyungmin Lee, Yoonsoo Kim, KyungAh Kim, Changmin Lee and Won Woo Ro, Won Woo Ro, “Measuring Error-Tolerance in SRAM Architecture on Hardware Accelerated Neural Network,” in the 1st IEEE/IEIE International Conference on Consumer Electronics (ICCE) Asia.


  • Ki Bum Chun, Changmin Lee, Won Woo Ro, “A Frequency Scaling Model for Energy Efficient DVFS Designs based on Circuit Delay Optimization,” in the 19th IEEE International Symposium on Consumer Electronics (ISCE), Madrid, Spain, Jun. 24 – 26, 2015.
  • Seung Hun Kim, Dohoon Kim, Changmin Lee, Won Seob Jeong, Won Woo Ro, and Jean-Luc Gaudiot, “A Performance-Energy Model to Evaluate Single Thread Execution Acceleration,” IEEE Computer Architecture Letters, Vol.14, No.2, pp. 99-102, Dec. 2015.


  • Keunsoo Kim, Changmin Lee, Jung Ho Jung, and Won Woo Ro, “Workload Synthesis: Generating Benchmark Workloads from Statistical Execution Profile,” in the 2014 IEEE International Symposium on Workload Characterization (IISWC 2014), Raleigh, North Carolina, Oct. 26 – 28, 2014.
  • Changmin Lee, Keunsoo Kim, Jung Ho Jung, and Won Woo Ro, “A Micro-benchmark Suite to Understand Micro-Architectural Differences between Processors,” in the 29th International Technical Conference on Circuit/Systems Computers and Communications (ITC-CSCC 2014), Phuket, Thailand, Jul. 1 – 4, 2014.
  • Jung Ho Jung, Seung Hun Kim, Changmin Lee, and Won Woo Ro, “Maximizing DRAM Performance using Selective Operating Frequency Boosting,” in the 18th IEEE International Symposium on Consumer Electronics (ISCE), Jeju, South Korea, Jun. 22 – 25, 2014.


  • Hyunkyu Park, Changmin Lee, Seung Hun Kim, Won Woo Ro, and Jean-Luc Gaudiot, “Mark-Sharing: A Parallel Garbage Collection Algorithm for Low Synchronization Overhead,” in the 19th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2013), Seoul, Korea, Dec. 15 – 18, 2013.
  • Deokho Kim, Changmin Lee, Sangpil Lee, and Won W. Ro, “Parallelized Sub-Resource Loading for Web Rendering Engine,” Journal of Systems Architecture, Volume 59, Issue 9, Pages 785-793, Oct. 2013.
  • Changmin Lee, Won Woo Ro, and Jean-Luc Gaudiot, “Boosting CUDA Applications with CPU-GPU Hybrid Computing,” International Journal of Parallel Programming (IJPP), Vol. 42, No. 2, pp. 384-404, Apr. 2014. (Note: this paper is an extension of our INTERACT-16 paper which has been selected as one of the best papers and recommended to IJPP.)
  • Hyunkyu Park, Changmin Lee, and Won W. Ro, “Parallel Garbage Collection with Transactional Memory,” in the 12th International Conference on Electronics, Information and Communication (ICEIC 2013), Bali, Indonesia, Jan. 30 – Feb. 2, 2013.


  • Seung Hun Kim, Changmin Lee, Keunsoo Kim, and Won W. Ro, “Offloading of Media Transcoding for High-Quality Multimedia Services,” Consumer Electronics, IEEE Transactions on, vol.58, no.2, pp.691-699, May 2012.
  • Changmin Lee, Won W. Ro, and Jean-Luc Gaudiot, “Cooperative Heterogeneous Computing for Parallel Processing on CPU/GPU Hybrids,” in the 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT-16), held in conjunction with HPCA-18, New Orleans, USA, Feb. 25 – 29, 2012.


  • Doohwan Oh, Sangpil Lee, Deokho Kim, Changmin Lee, and Won W. Ro, “Development of Virtual CUDA Systems for Parallel Processing on CPU and GPGPU,” in Workshop on Micro Architectural Support for Virtualization, Data Center Computing, and Clouds, held with the 43th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43), 2010.
Last modified on June 2, 2018